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Signal Integrity "Right by Design"

This two day advanced simulation and signal integrity seminar will consider the “Right by Design” approach to the design of high performance SDRAM memory systems (including DDR and DDR2 modes) and Gigabit digital transmission. The approach is based on transmission line fundamentals, SPICE and other simulation and timing tools and considers real world problems and solutions. Case studies and examples of real-world components and materials will be used throughout. Some consideration will also be given to the EMC/EMI effects to be expected from these high performance designs.

PWB Transmission Line Design Topics – Impedance and Cross-talk Predictions for Single-ended and Differential Transmission Lines
Lumped elements and loading in a transmission line environment
DDR and DDR2 architectures and SDRAM timing models, parameter variables and signal integrity issues
DDR and DDR2 READ and WRITE timing, set-up and hold margin analysis
Lossy Transmission Line Formulation and Modeling (the .W model)
Gigabit backplane, Infiniband and mezzanine board-to-board MSA connector characteristics and performance
Gigabit Transmission Limits of FR-4 and other PWB materials
Successful Design of OC-48/2.5 and 3.125 Gbps interconnect case studies
Gigabit equalization – analog passive cable and active digital single bit, multi-level and bandwidth modifying equalization
Gigabit Interoperability case study
EMI considerations in the design of Gigabit backplane and cable systems.

For further details see: www.conted.ox.ac.uk/ousep

Contact Oxford University Technology - Electronics, Telecoms and Engineering Programme